`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/24 10:52:28
// Design Name: 
// Module Name: bus_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module bus_tb;
    wire [15:0] data_bus;
    reg clk;
    reg data_in_en_A;
    reg data_out_en_A;
    reg data_in_en_B;
    reg data_out_en_B;
    reg data_in_en_C;
    reg data_out_en_C;
    reg rst_n;

    register reg_A(
        .clk(clk),
        .data_in_en(data_in_en_A),
        .data_out_en(data_out_en_A),
        .data_bus(data_bus),
        .rst_n(rst_n)
    );

    register reg_B(
        .clk(clk),
        .data_in_en(data_in_en_B),
        .data_out_en(data_out_en_B),
        .data_bus(data_bus),
        .rst_n(rst_n)
    );

    register reg_C(
        .clk(clk),
        .data_in_en(data_in_en_C),
        .data_out_en(data_out_en_C),
        .data_bus(data_bus),
        .rst_n(rst_n)
    );
    reg [6:0] rom_addr;
    reg write_en=0;
    assign data_bus =write_en ? 16'h1234 : 16'hzzzz;
    initial begin
        clk = 0;
        rst_n = 0;
        rom_addr = 0;
        data_in_en_A = 0;
        data_out_en_A = 0;
        data_in_en_B = 0;
        data_out_en_B = 0;
        data_in_en_C = 0;
        data_out_en_C = 0;
        #10 rst_n = 1;
        #10 data_in_en_A = 1;
        write_en=1;
        #10 write_en = 0;
        data_in_en_A = 0;
        #10 data_out_en_A = 1;
        data_in_en_B = 1;
        #10 data_out_en_A =0;
        data_in_en_B = 0;
        #10 $finish;
    
    end

    always #5 clk = ~clk;
    always @(posedge clk ) begin
        if (rom_addr==128) begin
            rom_addr<=0;
        end else begin
            rom_addr <= rom_addr + 1;
        end
        
    end
    rom_ip romm (
    .clka(clk),    // input wire clka
    .addra(rom_addr)  // input wire [6 : 0] addra
    );

endmodule
